The electrical connections between portions of semiconductor devices may be provided by wires attached to wire bond pads. For example, wire bonding may be used for making interconnections between an integrated circuit (IC) or another semiconductor device and its packaging during semiconductor device fabrication. Wire bonding may also be used to connect an IC to other electronics or to connect from one printed circuit board (PCB) to another. Wire bonding is generally considered to be a very cost-effective and flexible interconnect technology, and is used to assemble a majority of semiconductor packages.
Bond wires may be formed of one or more of several materials, for example, aluminum, copper, and gold. Bond wire diameters may be relatively small, for example, on the order of 15 μm, and may increase to several hundred micrometers, for example, for high-powered applications. Several techniques may be used to attach the bond wires to the bond pads, for example, ball bonding, wedge bonding, and compliant bonding. Ball bonding is generally reserved to gold and copper wire and usually requires heat. Wedge bonding can use either gold or aluminum wire, with only the gold wire requiring heat. In general, the wire is attached at both ends using some combination of heat, pressure, and/or ultrasonic energy to make a weld.
Wire bond pads currently use planar technology, resulting in the wire bond extending above the top layer of the semiconductor die being wire bonded. As shown by FIG. 1, wire bonding may be used to electrically connect electrical components on different layers of a multi-layer package 100. For example, a first wire bond pad 135 provides an electrical attachment surface for a photo sensor 150 on a first die layer 110 of the multi-layer package 100. A second wire bond pad 195 provides an electrical attachment surface for a second die layer or substrate layer 190 of the multi-layer package 100. The first wire bond pad 135 and the second wire bond pad 195 are electrically connected by a bond wire 170. The bonding of the bond wire 170 to the first bond pad 135 generally results in portions of the bond wire “loop” 190 extending significantly above the surface of the first bond pad 135, and likewise, above the top surface of the first die layer 110. This protrusion of the wire loop may impede full areal access over the wafer or die 110 by optics such as lenses, filters, encapsulation epoxies and compounds, scintillator crystals, and the like.
In some light detection applications, two or more silicon light-detection chips are placed side-by-side to form an array of light detectors. Examples of such light detecting arrays include medical imaging devices and astronomical telescope detectors. The light detecting array may include a matrix of chips, for example, a three-by-three array, or four-by four array. It may be desirable to pack the chips of this array is as closely as possible to maximize the light-detection active area relative to the mechanical dimensions of the array.
Photo detector chips generally have a chip outline or perimeter and an active detection area within the chip outline. Generally, a first electrical output connection connects to a chip die on the underside of the chip and a second electrical connection connects the chip to a specific contact area of a pad on the top side of the chip. The chips that form an array may be individually packaged and selected after testing, for example, based on certain performance specifications. The individual package includes a semiconductor chip bonded onto a substrate layer. This substrate can be a sub-mount for each chip that mounts to a second plate or tile for the array. Alternatively, the chip may mount directly to the substrate which is a single tile directly holding all of the chips in the array. In each of these examples, the chip is attached to its respective substrate using an electrically conductive bonding medium such as a backside contact, and a gold wire or similar bonding the chip top contact to another electrical contact area on the substrate. The substrate provides electrical tracking and contacts to an external device, so that each of the chips in the array can eventually be connected to suitable electronic systems nearby the detector array tile, such as amplifiers, bias voltage and voltage supplies, among others. The chip may then be over molded, for example, using an appropriate optically transparent epoxy compound, either individually on its sub-mount, or collectively with all the other chips on the tile, or both, once the surmounts are placed on their tile plate.
Typical chip layouts of this type may include an active area, an edge area and the area reserved for top-side contact pad. The top-side contact pad is typically 100 um in dimension, round, rectangular or square, with a thin bond wire ultrasonically welded to this pad. The other end of the wire may be bonded to the sub-mount or substrate adjacent to the pad. With this arrangement a relatively wide area of the surface must be allocated on the chip itself to fit this pad area next to the active area, and a corresponding wide area on the substrate for the wire. However, such an arrangement leaves a relatively high percentage of the chip array face area reserved for optically active area and for corresponding light radiation detection.
One solution for maximizing the active area to substrate surface area ratio is called a “Through-silicon via” or TSV, where the top-side contact is made by metallization tracks deposited on the silicon to the top end of a via-type metal or conductive contact “rod” synthesized within the silicon chip from top to bottom (the TSV). The contact to the substrate is then made through the bottom end of the via, possibly with metal contacts, for example, bump contacts, on the chip underside. The via may be placed under or next to the active area of the chip and thereby takes up little or no active area surface space, and yet allows the contact to top and bottom to occur more or less within the active area of the chip. Unfortunately, the TSV and bump contacts involve a complex and costly set of processes for silicon chip makers to perform and the processing of the silicon to form the vias and so forth can be detrimental to the operation of the photo-detector on the chip in any case.
Therefore, there is need in the industry to address at least some of the abovementioned shortcomings.